HCLTech is seeking a highly talented STA Engineer to drive static timing analysis and timing closure across block and full-chip designs. You will use PrimeTime, PT-SI, and PBA to sign off timing, develop SDC constraints, and implement MMMC analysis, with focus on cross-domain timing paths and clock architectures.
The role requires robust scripting in TCL and Python to automate STA workflows, debug timing ECOs, and contribute to tape-out readiness, while collaborating with Physical Design and RTL