Ready to help build the future of connectivity from space?
We're looking for a Senior FPGA Engineer to join a groundbreaking satellite communications program supporting next-generation Low Earth Orbit (LEO) satellite technology.
This is a unique opportunity to work on advanced phased-array payload hardware that will power one of the world's most ambitious satellite networks.In this role, you'll be much more than an FPGA designer.
You'll work directly with hardware in the lab, taking designs from concept through RTL development, implementation, timing closure, hardware bring-up, and validation.
This is a highly hands-on engineering opportunity where your work will contribute to technology that operates in space.Key ResponsibilitiesDesign and develop FPGA RTL using Verilog, SystemVerilog, or VHDLImplement and optimize high-speed interfaces including JESD204, PCIe, Aurora, and EthernetDrive timing closure, clocking architecture, constraints,



and performance optimizationPerform board bring-up, hardware validation, and debugging using JTAG, ILA, ChipScope, SignalTap, and lab equipmentDevelop FPGA solutions for high-speed data movement and communications between custom silicon devicesPrototype recent capabilities for future ASIC development effortsCollaborate closely with board design, systems, validation, and hardware engineering teamsWhat We're Looking For8+ years of FPGA/RTL development experienceStrong expertise in Verilog, SystemVerilog, and/or VHDLExperience with high-speed serial protocols and FPGA transceiversProven success with timing closure on complex FPGA designsHands-on hardware debugging and board bring-up experienceExperience with AMD/Xilinx or Intel/Altera FPGA platforms
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📌 Fpga Engineer (Western Australia)
🏢 GCS
📍 Western Australia