Ready to help build the future of connectivity from space?
We're looking for a Senior FPGA Engineer to join a groundbreaking satellite communications program supporting next-generation Low Earth Orbit (LEO) satellite technology.
This is a unique opportunity to work on advanced phased-array payload hardware that will power one of the world's most ambitious satellite networks.
In this role, you'll be much more than an FPGA designer.
You'll work directly with hardware in the lab, taking designs from concept through RTL development, implementation, timing closure, hardware bring-up, and validation.
This is a highly hands-on engineering prospect where your work will contribute to technology that operates in space.
Key Responsibilities
Design and develop FPGA RTL using Verilog, SystemVerilog, or VHDL
Implement and optimize high-speed interfaces including JESD204, PCIe, Aurora, and Ethernet
Drive timing closure, clocking architecture, constraints,



and performance optimization
Perform board bring-up, hardware validation, and debugging using JTAG, ILA, ChipScope, SignalTap, and lab equipment
Develop FPGA solutions for high-speed data movement and communications between custom silicon devices
Prototype new capabilities for future ASIC development efforts
Collaborate closely with board design, systems, validation, and hardware engineering teams
What We're Looking For
8+ years of FPGA/RTL development experience
Strong expertise in Verilog, SystemVerilog, and/or VHDL
Experience with high-speed serial protocols and FPGA transceivers
Proven success with timing closure on complex FPGA designs
Hands-on hardware debugging and board bring-up experience
Experience with AMD/Xilinx or Intel/Altera FPGA platforms

📌 Fpga Engineer (Western Australia)
🏢 GCS
📍 Western Australia