Optiver is offering a 10-week FPGA Developer Intern in Sydney to learn from seasoned hardware engineers and work on latency-critical trading systems. You will pair with a mentor, design rapid real-time systems, implement in VHDL/Verilog, and build test benches with SystemVerilog, while gaining exposure to network acceleration and market data processing. Successful interns may receive a full-time graduate offer and growth opportunities within Optiver's competitive engineering culture.