Apple is seeking an outstandingly hardworking design verification engineer to develop pre-silicon verification for IP designs.
You will craft test plans, build scalable verification settings, and drive regression analysis using SystemVerilog/UVM and LLMs to improve quality and efficiency.You will work on first silicon for IP blocks, develop verification plans, and report DV progress with metrics across bugs and coverage.
A solid background in DV methodology is required.
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📌 Design Verification Engineer – Soc Pre Silicon Systemverilog/uvm Melbourne (Australia)
🏢 Apple
📍 Australia
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