Baya Systems – Design Verification Engineer

England, UK (Bristol, Cambridge, London)

Responsibilities

- Create test plans for highly configurable IPs that provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems.
- Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
- Collaborate with software teams to define and implement configurable testbenches.
- Work with design teams on test plans, failure debugging, and coverage analysis.

Qualifications and Preferred Skills

- BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
- 8+ years of hands‑on experience in block‑level, IP‑level, or SoC‑level verification.
- Proficiency in Verilog and SystemVerilog.
- Familiarity with industry‑standard EDA tools for simulation and debugging.




- Deep experience with UVM‑based testbenches.
- Experience with modern programming languages such as Python.
- Knowledge of ARM AMBA protocols (AXI, APB, AHB) and, preferably, ARM CHI protocol.
- Experience working with IPs for caches, cache coherency, memory subsystems, interconnects, and NoCs.
- Knowledge of formal verification techniques and emulation platforms is a plus.
- Excellent problem‑solving skills and attention to detail.
- Solid communication and collaboration skills.

Compensation

- Salary commensurate with experience.
- Performance incentives.
- Comprehensive medical, dental, and vision benefits.
- 401(k) retirement plan.
- Equity.

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📌 Hardware Verification Engineer (Town of Cambridge)
🏢 Baya Systems
📍 Town of Cambridge