Apple Inc. in Melbourne is seeking a design verification engineer to ensure bug-free first silicon for IP and SoC blocks. You will craft verification methodology, test plans, and scalable environments to validate complex designs.
You will develop verification environments, including stimulus, checkers, assertions, trackers, and coverage metrics, while leveraging LLMs to improve efficiency and quality. Robust SystemVerilog/UVM experience and a 10+ year background are expected.
📌 Senior DV Engineer (Melbourne)
🏢 Apple
📍 Melbourne
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