16 Oct
|
SpaceX
|
Western Australia
16 Oct
SpaceX
Western Australia
SpaceX is seeking a Sr.
RTL Design Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink.
You will work with cross‐disciplinary teams—systems, firmware, architecture, design, validation, and ASIC implementation—to deliver high‐reliability chips for space and ground networks.
You will define micro-architecture, write RTL in Verilog/SystemVerilog, ensure full verification, and collaborate with the verification team to meet strict timing and synthesis goals.
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📌 Senior Rtl Design Engineer – Space-Grade Asics (Western Australia)
🏢 SpaceX
📍 Western Australia