SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink.
You will work with cross‑disciplinary teams—systems, firmware, architecture, design, validation, and ASIC implementation—to deliver high‑reliability chips for space and ground networks. You will define micro-architecture, write RTL in Verilog/SystemVerilog, ensure full verification, and collaborate with the verification team to meet strict timing and synthesis goals.