Job Description
Required Skills:n
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Expert‐level verification engineer with robust SystemVerilog and/ or UVM experience or
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FPGA verification in lab testing and/or Hardware FPGA design verification testing
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Experience with design on Xilinx products would be a strong plus
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expected to communicate effectively with emerging engineers at the India GETC‐I site and provide both technical and process (DO-254) guidance to the verification team.
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Core Responsibilitiesn
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RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
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Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
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Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. 1
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Key Qualificationsn
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Experience: Substantial hands‐on FPGA or ASIC development experience (typically 5+ years for a senior designation).
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Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.
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