Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our cutting-edge products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability.

Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company!

Your responsibilities would include:

- Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support.
- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
- Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean
- Develop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing.
- Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits.
- Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows.
- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test-mode/pin-mux control.
- Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
- Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring-up/debug.
- Drive silicon debug, yield analysis, DFT scripting / automation,



and cross-functional collaboration with frontend, verification, PnR, and ATE in fast-paced tapeout programs.

Essential skills (you must have):

- Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science
- 5+ years experience as a DFT Engineer
- Strong hands-on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
- Solid understanding of digital design fundamentals, including RTL coding and verification
- Proven expertise on hierarchical DFT methodologies is a plug
- Post-silicon debug and silicon bring-up experience
- Excellent verbal and written communication skills
- Proven to work constructively within your team and among other groups
- Strong analytical and problem-solving skills
- A determination to deliver even when subject to time pressures
- A hands-on, practical attitude

What we offer:

- Competitive salary + excellent stock option package
- Performance Bonus opportunity
- Income protection Insurance
- Healthy work environment with sit/stand desks and large screens
- Lots of snacks & drinks, including barista coffee, Friday team lunches & some of the world’s best beers
- Work from home policy
- Community & social groups and much more
- Join a high performing, inclusive company where you can make a real impact

Who we are:

Morse Micro is Australia’s largest semiconductor company building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate, and invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney, Picton & Melbourne (Australia), Irvine, Bay Area & Boston (USA), Bangalore (India), Cambridge (UK), Hangzhou (China), Taipei (Taiwan) and Tokyo (Japan).

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📌 Senior DFT Engineer: Remote, Stock Options, High-Impact (Picton)
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