Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity.
Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability.Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)?
Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun setting?
Then join Morse Micro, Australia's largest fabless semiconductor company!
We welcome applications from overseas candidates, with relocation and visa support available for the successful applicant.Your responsibilities would include:Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support.Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.Architect and implement SCAN solutions, including chains, sub-chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC cleanDevelop and integrate at-speed test methodologies using OPCG for intra- and inter-clock domain testing.Implement low-power DFT techniques such as power-aware scan, clock staggering, and test-point insertion to meet ATE/package limits.Own MBIST integration and diagnostics for all on-chip memories, including JTAG-based debug diagnostic flows.Implement and maintain IEEE ****** JTAG/TAP, BSDL, IEEE **** wrappers, and DFT test-mode/pin-mux control.Integrate DFT for third-party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.Generate and validate ATPG (stuck-at, transition, path-delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL,



and support first silicon ATE bring-up/debug.Drive silicon debug, yield analysis, DFT scripting / automation, and cross-functional collaboration with frontend, verification, PnR, and ATE in fast-paced tapeout programs.Essential skills (you must have):Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science5+ years experience as a DFT EngineerStrong hands-on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysisSolid understanding of digital design fundamentals, including RTL coding and verificationProven expertise on hierarchical DFT methodologies is a plugPost-silicon debug and silicon bring-up experienceExcellent verbal and written communication skillsProven to work constructively within your team and among other groupsStrong analytical and problem-solving skillsA determination to deliver even when subject to time pressuresA hands-on, practical attitudeWhat we offer:Competitive salary + excellent stock option packagePerformance Bonus opportunityIncome protection InsuranceHealthy work environment with sit/stand desks and large screensLots of snacks & drinks, including barista coffee, Friday team lunches & some of the world's best beersFlexible working hoursWork from home policyCommunity & social groups and much moreJoin a high performing, inclusive company where you can make a real impactWho we are:Morse Micro is Australia's largest semiconductor company building Wi-Fi HaLow *******ah) chips for the Internet of Things (IoT).
We are a team of wireless experts that love to work hard, innovate & invent.
Together, we are building the world's lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet.
We are a global team with offices in Sydney, Picton & Melbourne (Australia), Irvine & San Jose (USA), Bangalore (India), Cambridge (UK), Hangzhou & Shenzen (China), Taipei (Taiwan) and Tokyo (Japan).

📌 Senior Dft Engineer (Sydney)
🏢 Morse Micro
📍 Sydney