Job Description
Overview
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Flight software (FSW) engineers write the software that runs on a spacecraft's radiation‐hardened processor. Their work includes attitude control loops, fault‐protection algorithms, command and telemetry managers, payload sequencers, memory scrubbers, and uplink/downlink protocol stacks.
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Responsibilities
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Write software for radiation‐hardened processors under real‐time operating systems such as VxWorks 653, RTEMS, FreeRTOS, or NASA's Core Flight System (cFS).
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Design and implement attitude‐control loops, fault‐protection algorithms, command and telemetry managers, payload sequencers, memory scrubbers, and uplink/downlink protocol stacks.
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Use formal‐methods techniques (SPARK Ada proofs, Frama‐C static analysis), model‐based design
(Simulink/Stateflow
auto‐code generation), and rigorous unit and integration testing (GMock, Cantata++, VectorCAST).
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Maintain traceability from requirements to code using DOORS and conduct peer reviews and configuration‐management tasks.
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Conduct hardware‐in‐the‐loop simulation and validate software against flight‐hardware models.
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Qualifications
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Bachelor's degree in Computer Science, Software Engineering, Electrical Engineering, or a related field.
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Master's degree in Real‐Time Embedded Systems, Computer Engineering, or Aerospace Engineering is preferred.
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Proficiency in C or C++; experience with Ada/SPARK is a plus.
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Hands‐on experience programming for real‐time operating systems (VxWorks 653, RTEMS, FreeRTOS, cFS).
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Familiarity with formal‐verification tools, model‐based code generation, and static‐analysis tools.
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Experience with DOORS traceability, unit/integration testing frameworks (GMock, Cantata++, VectorCAST), and HIL simulation.
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Minimum 3–5 years of relevant industry or research experience; a solid senior/lead background (5+ years) is desirable.
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Key Skills
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Embedded C/C++ programming
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Real‐time scheduler theory (Rate‐Monotonic, EDF)
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Formal verification (SPARK Ada, Frama‐C)
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Model‐based design and automatic code generation
(Simulink/Stateflow)
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Static analysis and software‐testing tools (VectorCAST, Cantata++, LDRA)
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Hardware‐in‐the‐loop simulation
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DOORS traceability and configuration‐management
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Space communication protocols (CCSDS, SpaceWire RMAP)
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Salary (U.S.)
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Entry level (0–3 years): $*******. Median (4–8 years): $*******. Senior (9+ years): $*******. (US‐centric estimates; international compensation varies.)
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Global Opportunities
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NASA (USA)
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ESA/ESTEC (Europe)
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CNES (France)
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DLR (Germany)
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ISRO (India)
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JAXA (Japan)
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MDA Space (Canada)
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KARI (South Korea)
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Satrec Initiative (South Korea)
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Reality Check
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Good fit if:
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You find formal verification or proof‐of‐correctness intellectually rewarding.
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You are comfortable doing code review on safety‐critical C where a single missing bounds check could destroy a mission.
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You enjoy working at the boundary of software and hardware—reading datasheets, writing device drivers, and debugging with a logic analyser.
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Bad fit if:
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You want modern web‐style development practices; this role has no Docker, no CD pipelines, and 18‐month qualification cycles for a 200‐line change.
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You find process documentation (SRS, SDD, test reports per ECSS‐E‐ST‐40C or NASA‐STD‐******) bureaucratic and demotivating.
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You are motivated primarily by performance optimisation; FSW correctness constraints often prevent elegant algorithmic solutions.
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#J-*****-Ljbffr

📌 Flight Software Engineer (South Australia)
🏢 UNKNOWN
📍 South Australia