Job Description

Morse Micro is at the forefront of next-generation Wi‐Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability.

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Do you want to play a key role in building next generation Wi‐Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC‐backed high‐growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia's largest fabless semiconductor company!

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We welcome applications from overseas candidates, with relocation and visa support available for the successful applicant.

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Your responsibilities would include:

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- Own end-to-end DFT for wireless SoCs, including architecture, implementation, verification, tapeout sign-off, silicon bring-up, and production support.
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- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
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- Architect and implement SCAN solutions, including chains, sub‐chains, masking, compressors, decompressors, SDCs, and ensure post synthesis SCAN DRC clean
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- Develop and integrate at‐speed test methodologies using OPCG for intra‐ and inter‐clock domain testing.
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- Implement low‐power DFT techniques such as power‐aware scan, clock staggering, and test‐point insertion to meet ATE/package limits.
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- Own MBIST integration and diagnostics for all on‐chip memories, including JTAG‐based debug diagnostic flows.
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- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test‐mode/pin‐mux control.
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- Integrate DFT for third‐party hardened IPs (e.g. PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
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- Generate and validate ATPG (stuck‐at, transition, path‐delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring‐up/debug.
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- Drive silicon debug, yield analysis, DFT scripting / automation, and cross‐functional collaboration with frontend, verification, PnR, and ATE in fast‐paced tapeout programs.
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Essential skills (you must have):

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- Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science
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- 5+ years experience as a DFT Engineer
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- Solid hands‐on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
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- Solid understanding of digital design fundamentals, including RTL coding and verification
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- Proven expertise on hierarchical DFT methodologies is a plug
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- Post‐silicon debug and silicon bring‐up experience
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- Excellent verbal and written communication skills
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- Proven to work constructively within your team and among other groups
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- Strong analytical and problem‐solving skills
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- A determination to deliver even when subject to time pressures
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- A hands‐on, practical attitude
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What we offer:

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- Competitive salary + excellent stock option package
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- Performance Bonus opportunity
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- Income protection Insurance
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- Healthy work environment with sit/stand desks and large screens
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- Lots of snacks & drinks, including barista coffee, Friday team lunches & some of the world's best beers
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- Flexible working hours
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- Work from home policy
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- Community & social groups and much more
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- Join a high performing, inclusive company where you can make a real impact
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Who we are:

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Morse Micro is Australia's largest semiconductor company building Wi‐Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate & invent. Together, we are building the world's lowest power Wi‐Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney, Picton & Melbourne (Australia), Irvine & San Jose (USA), Bangalore (India), Cambridge (UK), Hangzhou & Shenzen (China), Taipei (Taiwan) and Tokyo (Japan).

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📌 Senior DFT Engineer (New South Wales)
🏢 Matchbox
📍 New South Wales