Job Description
Overview
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Morse Micro is a leading manufacturer of next‐generation Wi‐Fi technology, focused on building 802.11ah chips for the Internet of Things.
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Responsibilities
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- Own end‐to‐end DFT for wireless SoCs, including architecture, implementation, verification, tape‐out sign‐off, silicon bring‐up, and production support.
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- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
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- Architect and implement SCAN solutions, including chains, sub‐chains, masking, compressors, decompressors, SDCs, and ensure post‐synthesis SCAN DRC cleanliness.
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- Develop and integrate at‐speed test methodologies using OPCG for intra‐ and inter‐clock domain testing.
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- Implement low‐power DFT techniques such as power‐aware scan, clock staggering, and test‐point insertion to meet ATE/package limits.
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- Own MBIST integration and diagnostics for all on‐chip memories, including JTAG‐based debug diagnostic flows.
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- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test‐mode/pin‐mux control.
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- Integrate DFT for third‐party hardened IPs (e.g., PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
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- Generate and validate ATPG (stuck‐at, transition, path‐delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring‐up/debug.
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- Drive silicon debug,
yield analysis, DFT scripting/automation, and cross‐functional collaboration with frontend, verification, PnR, and ATE in quick‐paced tape‐out programs.
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Essential Skills
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- BSc/MSc/PhD in Electrical, Electronics, Communication Engineering, or Computer Science
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- 5+ years experience as a DFT Engineer
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- Strong hands‐on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
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- Solid understanding of digital design fundamentals, including RTL coding and verification
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- Proven expertise on hierarchical DFT methodologies is a plug
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- Post‐silicon debug and silicon bring‐up experience
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- Excellent verbal and written communication skills
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- Proven ability to work constructively within a team and with other groups
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- Strong analytical and problem‐solving skills
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- A determination to deliver even under time pressures
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- A hands‐on, practical attitude
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Benefits
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- Competitive salary and excellent stock option package
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- Performance bonus opportunity
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- Income protection insurance
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- Healthy work environment with sit/stand desks and large screens
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- Snacks & drinks, including barista coffee and Friday team lunches
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- Work‐from‐home policy
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- Community and social groups and much more
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- Join a high‐performing, inclusive company where you can make a real impact
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📌 Senior DFT Engineer: Remote, Stock Options, High-Impact (Picton)
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