21 Aug
|
Fi NOW
|
Razorback
Job Description
n Overviewn
Morse Micro is a leading manufacturer of next‑generation Wi‑Fi technology, focused on building 802.11ah chips for the Internet of Things.
Responsibilitiesn
n
- Own end‑to‑end DFT for wireless SoCs, including architecture, implementation, verification, tape‑out sign‑off, silicon bring‑up, and production support.
n
- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
n
- Architect and implement SCAN solutions, including chains, sub‑chains, masking, compressors, decompressors, SDCs, and ensure post‑synthesis SCAN DRC cleanliness.
n
- Develop and integrate at‑speed test methodologies using OPCG for intra‑ and inter‑clock domain testing.
n
- Implement low‑power DFT techniques such as power‑aware scan, clock staggering, and test‑point insertion to meet ATE/package limits.
n
- Own MBIST integration and diagnostics for all on‑chip memories, including JTAG‑based debug diagnostic flows.
n
- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test‑mode/pin‑mux control.
n
- Integrate DFT for third‑party hardened IPs (e.g., PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
n
- Generate and validate ATPG (stuck‑at, transition, path‑delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring‑up/debug.
n
- Drive silicon debug,
yield analysis, DFT scripting/automation, and cross‑functional collaboration with frontend, verification, PnR, and ATE in rapid‑paced tape‑out programs.
n
Essential Skillsn n
- BSc/MSc/PhD in Electrical, Electronics, Communication Engineering, or Computer Science
n
- 5+ years experience as a DFT Engineer
n
- Strong hands‑on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
n
- Solid understanding of digital design fundamentals, including RTL coding and verification
n
- Proven expertise on hierarchical DFT methodologies is a plug
n
- Post‑silicon debug and silicon bring‑up experience
n
- Excellent verbal and written communication skills
n
- Proven ability to work constructively within a team and with other groups
n
- Strong analytical and problem‑solving skills
n
- A determination to deliver even under time pressures
n
- A hands‑on, practical attitude
n
Benefitsn n
- Competitive salary and excellent stock option package
n
- Performance bonus opportunity
n
- Income protection insurance
n
- Healthy work environment with sit/stand desks and large screens
n
- Snacks & drinks, including barista coffee and Friday team lunches
n
- Work‑from‑home policy
n
- Community and social groups and much more
n
- Join a high‑performing, inclusive company where you can make a real impact
n
n
#J-18808-Ljbffr
📌 Senior DFT Engineer: Remote, Stock Options, High-Impact (Razorback)
🏢 Fi NOW
📍 Razorback