Senior DFT Engineer (Picton)

Senior DFT Engineer (Picton)

02 Aug
|
Fi NOW
|
Picton

02 Aug

Fi NOW

Picton

Overview

Morse Micro is a leading manufacturer of next‑generation Wi‑Fi technology, focused on building 802.11ah chips for the Internet of Things.

Responsibilities

- Own end‑to‑end DFT for wireless SoCs, including architecture, implementation, verification, tape‑out sign‑off, silicon bring‑up, and production support.
- Define DFT architecture and coverage goals, optimizing test quality, pattern count, power, area, and tester time/constraints.
- Architect and implement SCAN solutions, including chains, sub‑chains, masking, compressors, decompressors, SDCs, and ensure post‑synthesis SCAN DRC cleanliness.
- Develop and integrate at‑speed test methodologies using OPCG for intra‑ and inter‑clock domain testing.
- Implement low‑power DFT techniques such as power‑aware scan, clock staggering, and test‑point insertion to meet ATE/package limits.
- Own MBIST integration and diagnostics for all on‑chip memories, including JTAG‑based debug diagnostic flows.
- Implement and maintain IEEE 1149.1 JTAG/TAP, BSDL, IEEE 1500 wrappers, and DFT test‑mode/pin‑mux control.
- Integrate DFT for third‑party hardened IPs (e.g., PLL, USB PHY, RRAM, FUSE), including wrapper design and vendor pattern integration.
- Generate and validate ATPG (stuck‑at, transition, path‑delay) and MBIST patterns, perform GLS with SDF, deliver WGL/STIL, and support first silicon ATE bring‑up/debug.
- Drive silicon debug,



yield analysis, DFT scripting/automation, and cross‑functional collaboration with frontend, verification, PnR, and ATE in fast‑paced tape‑out programs.

Essential Skills

- BSc/MSc/PhD in Electrical, Electronics, Communication Engineering, or Computer Science
- 5+ years experience as a DFT Engineer
- Strong hands‑on experience in scan insertion/stitching, ATPG setup, JTAG, simulation, debug, and scan DRC analysis
- Solid understanding of digital design fundamentals, including RTL coding and verification
- Proven expertise on hierarchical DFT methodologies is a plug
- Post‑silicon debug and silicon bring‑up experience
- Excellent verbal and written communication skills
- Proven ability to work constructively within a team and with other groups
- Strong analytical and problem‑solving skills
- A determination to deliver even under time pressures
- A hands‑on, practical attitude

Perks

- Competitive salary and excellent stock option package
- Performance bonus opportunity
- Income protection insurance
- Healthy work environment with sit/stand desks and large screens
- Snacks & drinks, including barista coffee and Friday team lunches
- Work‑from‑home policy
- Community and social groups and much more
- Join a high‑performing, inclusive company where you can make a real impact

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📌 Senior DFT Engineer (Picton)
🏢 Fi NOW
📍 Picton

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